Multi-port memories, such as dual-port SRAMs allow two operations, such as a read and a write, per clock cycle, thereby increasing bandwidth of the dual-port SRAMs to about 2× of single-port SRAMs. To implement a dual-port SRAM, each bit cell of the memory can have an additional port added thereto. However, transistors and wires for implementing the additional port for each bit cell occupy additional area. Furthermore, a read-disturb-write situation or a write-disturb-write situation can arise, for example, when a write operation occurs at one port, and a dummy read operation resulted from a read operation or a write operation of another cell in the same row occurs at the other port simultaneously. In contrast, a dual-port SRAM can be implemented using single-port SRAM cells with the single port shared by two operations in a time division multiplexed manner. In this way, the area efficiency is higher and the read-disturb-write and write-disturb-write situations are prevented.